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Abstract

This paper presents the design of the inter-integrated circuit (I2C) protocol with different types of features, such as combined messages, addressing modes, different data patterns and start addresses, clock frequencies, and types of modes between the field-programmable gate array (FPGA) and test card. Moreover, all these features can be randomized and run for long hours. The FPGA and the test card respectively act as master and slave. The design architecture comprises master and slave. The master generates a START condition, in which the serial data will transact between high to low levels and the serial clock will remain high. Then, the master also generates the STOP condition. Additionally, a few types of messaging modes, such as PIO read, PIO write, PIO write–read, and PIO read–write, are available. By contrast, the master also transfers and receives data to or from slave devices by using different addressing modes. The implemented addressing modes are 7 and 10 bits. This paper also focuses on randomizing the sent data byte and the start address. Particularly, data sending, reading, and writing operations are conducted and stimulated by capturing the signal using a logic analyzer. The signal is then examined and compared with the actual I2C protocol format. A stress test is performed by randomizing all the features and running for long hours (4 h). The stress test aims to stress the IP and ensure the health of IP.

Bahasa Abstract

Artikel ini menyajikan rancangan protokol inter-integrated circuit (I2C) dengan berbagai jenis fitur, seperti pesan gabungan, mode pengalamatan, pola data dan alamat awal yang berbeda, frekuensi clock, dan jenis mode antara field-programmable gate array (FPGA) dan kartu tes. Selain itu, semua fitur ini dapat diacak dan dijalankan selama berjam-jam. FPGA dan kartu tes masing-masing bertindak sebagai master dan slave. Arsitektur desain terdiri dari master dan slave. Master menghasilkan kondisi START, di mana data serial akan ditransaksikan antara tingkat tinggi ke rendah dan serial clock akan tetap tinggi. Kemudian, master juga membangkitkan kondisi STOP. Sebagai tambahan, tersedia beberapa jenis mode pesan, seperti PIO read, PIO write, PIO write–read, dan PIO read–write. Sebaliknya, master juga mentransfer dan menerima data ke atau dari perangkat slave dengan menggunakan mode pengalamatan yang berbeda. Mode pengalamatan yang diimplementasikan adalah 7 dan 10 bit. Artikel ini juga berfokus pada pengacakan bita data yang dikirim dan alamat awal. Khususnya, operasi pengiriman, pembacaan, dan penulisan data dilakukan dan dirangsang dengan menangkap sinyal menggunakan penganalisis logika. Sinyal tersebut kemudian diuji dan dibandingkan dengan format protokol I2C yang sebenarnya. Uji ketahanan dilakukan dengan mengacak semua fitur dan berjalan selama berjam-jam (4 jam). Uji ketahanan bertujuan untuk menekankan IP dan memastikan kesehatan IP.

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